Xenomai  3.0.5
rt2500pci.h
1 /* rt2500pci.h
2  *
3  * Copyright (C) 2004 - 2005 rt2x00-2.0.0-b3 SourceForge Project
4  * <http://rt2x00.serialmonkey.com>
5  * 2006 rtnet adaption by Daniel Gregorek
6  * <dxg@gmx.de>
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; either version 2 of the License, or
11  * (at your option) any later version.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16  * GNU General Public License for more details.
17  *
18  * You should have received a copy of the GNU General Public License
19  * along with this program; if not, write to the
20  * Free Software Foundation, Inc.,
21  * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22  */
23 
24 /*
25  * Module: rt2500pci
26  * Abstract: Data structures and registers for the rt2500pci module.
27  * Supported chipsets: RT2560.
28  */
29 
30 #ifndef RT2500PCI_H
31 #define RT2500PCI_H
32 
33 /*
34  * RT chip defines
35  */
36 #define RT2560 0x0201
37 
38 /*
39  * RF chip defines
40  */
41 #define RF2522 0x0200
42 #define RF2523 0x0201
43 #define RF2524 0x0202
44 #define RF2525 0x0203
45 #define RF2525E 0x0204
46 #define RF5222 0x0210
47 
48 /*
49  * Control/Status Registers(CSR).
50  */
51 #define CSR0 0x0000 /* ASIC revision number. */
52 #define CSR1 0x0004 /* System control register. */
53 #define CSR2 0x0008 /* System admin status register (invalid). */
54 #define CSR3 0x000c /* STA MAC address register 0. */
55 #define CSR4 0x0010 /* STA MAC address register 1. */
56 #define CSR5 0x0014 /* BSSID register 0. */
57 #define CSR6 0x0018 /* BSSID register 1. */
58 #define CSR7 0x001c /* Interrupt source register. */
59 #define CSR8 0x0020 /* Interrupt mask register. */
60 #define CSR9 0x0024 /* Maximum frame length register. */
61 #define SECCSR0 0x0028 /* WEP control register. */
62 #define CSR11 0x002c /* Back-off control register. */
63 #define CSR12 0x0030 /* Synchronization configuration register 0. */
64 #define CSR13 0x0034 /* Synchronization configuration register 1. */
65 #define CSR14 0x0038 /* Synchronization control register. */
66 #define CSR15 0x003c /* Synchronization status register. */
67 #define CSR16 0x0040 /* TSF timer register 0. */
68 #define CSR17 0x0044 /* TSF timer register 1. */
69 #define CSR18 0x0048 /* IFS timer register 0. */
70 #define CSR19 0x004c /* IFS timer register 1. */
71 #define CSR20 0x0050 /* WakeUp register. */
72 #define CSR21 0x0054 /* EEPROM control register. */
73 #define CSR22 0x0058 /* CFP Control Register. */
74 
75 /*
76  * Transmit related CSRs.
77  */
78 #define TXCSR0 0x0060 /* TX control register. */
79 #define TXCSR1 0x0064 /* TX configuration register. */
80 #define TXCSR2 0x0068 /* TX descriptor configuratioon register. */
81 #define TXCSR3 0x006c /* TX Ring Base address register. */
82 #define TXCSR4 0x0070 /* TX Atim Ring Base address register. */
83 #define TXCSR5 0x0074 /* TX Prio Ring Base address register. */
84 #define TXCSR6 0x0078 /* Beacon base address. */
85 #define TXCSR7 0x007c /* AutoResponder Control Register. */
86 #define TXCSR8 0x0098 /* CCK TX BBP registers. */
87 #define TXCSR9 0x0094 /* OFDM TX BBP registers. */
88 
89 /*
90  * Receive related CSRs.
91  */
92 #define RXCSR0 0x0080 /* RX control register. */
93 #define RXCSR1 0x0084 /* RX descriptor configuration register. */
94 #define RXCSR2 0x0088 /* RX Ring base address register. */
95 #define RXCSR3 0x0090 /* BBP ID register 0 */
96 #define ARCSR1 0x009c /* Auto Responder PLCP config register 1. */
97 
98 /*
99  * PCI control CSRs.
100  */
101 #define PCICSR 0x008c /* PCI control register. */
102 
103 /*
104  * Statistic Register.
105  */
106 #define CNT0 0x00a0 /* FCS error count. */
107 #define TIMECSR2 0x00a8
108 #define CNT1 0x00ac /* PLCP error count. */
109 #define CNT2 0x00b0 /* long error count. */
110 #define TIMECSR3 0x00b4
111 #define CNT3 0x00b8 /* CCA false alarm count. */
112 #define CNT4 0x00bc /* Rx FIFO overflow count. */
113 #define CNT5 0x00c0 /* Tx FIFO underrun count. */
114 
115 /*
116  * Baseband Control Register.
117  */
118 #define PWRCSR0 0x00c4 /* Power mode configuration. */
119 #define PSCSR0 0x00c8 /* Power state transition time. */
120 #define PSCSR1 0x00cc /* Power state transition time. */
121 #define PSCSR2 0x00d0 /* Power state transition time. */
122 #define PSCSR3 0x00d4 /* Power state transition time. */
123 #define PWRCSR1 0x00d8 /* Manual power control / status. */
124 #define TIMECSR 0x00dc /* Timer control. */
125 #define MACCSR0 0x00e0 /* MAC configuration. */
126 #define MACCSR1 0x00e4 /* MAC configuration. */
127 #define RALINKCSR 0x00e8 /* Ralink Auto-reset register. */
128 #define BCNCSR 0x00ec /* Beacon interval control register. */
129 
130 /*
131  * BBP / RF / IF Control Register.
132  */
133 #define BBPCSR 0x00f0 /* BBP serial control. */
134 #define RFCSR 0x00f4 /* RF serial control. */
135 #define LEDCSR 0x00f8 /* LED control register */
136 
137 #define SECCSR3 0x00fc /* AES control register. */
138 
139 /*
140  * ASIC pointer information.
141  */
142 #define RXPTR 0x0100 /* Current RX ring address. */
143 #define TXPTR 0x0104 /* Current Tx ring address. */
144 #define PRIPTR 0x0108 /* Current Priority ring address. */
145 #define ATIMPTR 0x010c /* Current ATIM ring address. */
146 
147 #define TXACKCSR0 0x0110 /* TX ACK timeout. */
148 #define ACKCNT0 0x0114 /* TX ACK timeout count. */
149 #define ACKCNT1 0x0118 /* RX ACK timeout count. */
150 
151 /*
152  * GPIO and others.
153  */
154 #define GPIOCSR 0x0120 /* GPIO. */
155 #define FIFOCSR0 0x0128 /* TX FIFO pointer. */
156 #define FIFOCSR1 0x012c /* RX FIFO pointer. */
157 #define BCNCSR1 0x0130 /* Tx BEACON offset time, unit: 1 usec. */
158 #define MACCSR2 0x0134 /* TX_PE to RX_PE delay time, unit: 1 PCI clock cycle. */
159 #define TESTCSR 0x0138 /* TEST mode selection register. */
160 #define ARCSR2 0x013c /* 1 Mbps ACK/CTS PLCP. */
161 #define ARCSR3 0x0140 /* 2 Mbps ACK/CTS PLCP. */
162 #define ARCSR4 0x0144 /* 5.5 Mbps ACK/CTS PLCP. */
163 #define ARCSR5 0x0148 /* 11 Mbps ACK/CTS PLCP. */
164 #define ARTCSR0 0x014c /* ACK/CTS payload consumed time for 1/2/5.5/11 mbps. */
165 #define ARTCSR1 0x0150 /* OFDM ACK/CTS payload consumed time for 6/9/12/18 mbps. */
166 #define ARTCSR2 0x0154 /* OFDM ACK/CTS payload consumed time for 24/36/48/54 mbps. */
167 #define SECCSR1 0x0158 /* WEP control register. */
168 #define BBPCSR1 0x015c /* BBP TX configuration. */
169 #define DBANDCSR0 0x0160 /* Dual band configuration register 0. */
170 #define DBANDCSR1 0x0164 /* Dual band configuration register 1. */
171 #define BBPPCSR 0x0168 /* BBP Pin control register. */
172 #define DBGSEL0 0x016c /* MAC special debug mode selection register 0. */
173 #define DBGSEL1 0x0170 /* MAC special debug mode selection register 1. */
174 #define BISTCSR 0x0174 /* BBP BIST register. */
175 #define MCAST0 0x0178 /* multicast filter register 0. */
176 #define MCAST1 0x017c /* multicast filter register 1. */
177 #define UARTCSR0 0x0180 /* UART1 TX register. */
178 #define UARTCSR1 0x0184 /* UART1 RX register. */
179 #define UARTCSR3 0x0188 /* UART1 frame control register. */
180 #define UARTCSR4 0x018c /* UART1 buffer control register. */
181 #define UART2CSR0 0x0190 /* UART2 TX register. */
182 #define UART2CSR1 0x0194 /* UART2 RX register. */
183 #define UART2CSR3 0x0198 /* UART2 frame control register. */
184 #define UART2CSR4 0x019c /* UART2 buffer control register. */
185 
186 /*
187  * EEPROM addresses
188  */
189 #define EEPROM_ANTENNA 0x10
190 #define EEPROM_GEOGRAPHY 0x12
191 #define EEPROM_BBP_START 0x13
192 #define EEPROM_BBP_END 0x22
193 
194 #define EEPROM_BBP_SIZE 16
195 
196 /*
197  * CSR Registers.
198  * Some values are set in TU, whereas 1 TU == 1024 us.
199  */
200 
201 /*
202  * CSR1: System control register.
203  */
204 #define CSR1_SOFT_RESET FIELD32(0, 0x00000001) /* Software reset, 1: reset, 0: normal. */
205 #define CSR1_BBP_RESET FIELD32(1, 0x00000002) /* Hardware reset, 1: reset, 0, release. */
206 #define CSR1_HOST_READY FIELD32(2, 0x00000004) /* Host ready after initialization. */
207 
208 /*
209  * CSR3: STA MAC address register 0.
210  */
211 #define CSR3_BYTE0 FIELD32(0, 0x000000ff) /* MAC address byte 0. */
212 #define CSR3_BYTE1 FIELD32(8, 0x0000ff00) /* MAC address byte 1. */
213 #define CSR3_BYTE2 FIELD32(16, 0x00ff0000) /* MAC address byte 2. */
214 #define CSR3_BYTE3 FIELD32(24, 0xff000000) /* MAC address byte 3. */
215 
216 /*
217  * CSR4: STA MAC address register 1.
218  */
219 #define CSR4_BYTE4 FIELD32(0, 0x000000ff) /* MAC address byte 4. */
220 #define CSR4_BYTE5 FIELD32(8, 0x0000ff00) /* MAC address byte 5. */
221 
222 /*
223  * CSR5: BSSID register 0.
224  */
225 #define CSR5_BYTE0 FIELD32(0, 0x000000ff) /* BSSID address byte 0. */
226 #define CSR5_BYTE1 FIELD32(8, 0x0000ff00) /* BSSID address byte 1. */
227 #define CSR5_BYTE2 FIELD32(16, 0x00ff0000) /* BSSID address byte 2. */
228 #define CSR5_BYTE3 FIELD32(24, 0xff000000) /* BSSID address byte 3. */
229 
230 /*
231  * CSR6: BSSID register 1.
232  */
233 #define CSR6_BYTE4 FIELD32(0, 0x000000ff) /* BSSID address byte 4. */
234 #define CSR6_BYTE5 FIELD32(8, 0x0000ff00) /* BSSID address byte 5. */
235 
236 /*
237  * CSR7: Interrupt source register.
238  * Write 1 to clear.
239  */
240 #define CSR7_TBCN_EXPIRE FIELD32(0, 0x00000001) /* beacon timer expired interrupt. */
241 #define CSR7_TWAKE_EXPIRE FIELD32(1, 0x00000002) /* wakeup timer expired interrupt. */
242 #define CSR7_TATIMW_EXPIRE FIELD32(2, 0x00000004) /* timer of atim window expired interrupt. */
243 #define CSR7_TXDONE_TXRING FIELD32(3, 0x00000008) /* tx ring transmit done interrupt. */
244 #define CSR7_TXDONE_ATIMRING FIELD32(4, 0x00000010) /* atim ring transmit done interrupt. */
245 #define CSR7_TXDONE_PRIORING FIELD32(5, 0x00000020) /* priority ring transmit done interrupt. */
246 #define CSR7_RXDONE FIELD32(6, 0x00000040) /* receive done interrupt. */
247 #define CSR7_DECRYPTION_DONE FIELD32(7, 0x00000080) /* Decryption done interrupt. */
248 #define CSR7_ENCRYPTION_DONE FIELD32(8, 0x00000100) /* Encryption done interrupt. */
249 #define CSR7_UART1_TX_TRESHOLD FIELD32(9, 0x00000200) /* UART1 TX reaches threshold. */
250 #define CSR7_UART1_RX_TRESHOLD FIELD32(10, 0x00000400) /* UART1 RX reaches threshold. */
251 #define CSR7_UART1_IDLE_TRESHOLD FIELD32(11, 0x00000800) /* UART1 IDLE over threshold. */
252 #define CSR7_UART1_TX_BUFF_ERROR FIELD32(12, 0x00001000) /* UART1 TX buffer error. */
253 #define CSR7_UART1_RX_BUFF_ERROR FIELD32(13, 0x00002000) /* UART1 RX buffer error. */
254 #define CSR7_UART2_TX_TRESHOLD FIELD32(14, 0x00004000) /* UART2 TX reaches threshold. */
255 #define CSR7_UART2_RX_TRESHOLD FIELD32(15, 0x00008000) /* UART2 RX reaches threshold. */
256 #define CSR7_UART2_IDLE_TRESHOLD FIELD32(16, 0x00010000) /* UART2 IDLE over threshold. */
257 #define CSR7_UART2_TX_BUFF_ERROR FIELD32(17, 0x00020000) /* UART2 TX buffer error. */
258 #define CSR7_UART2_RX_BUFF_ERROR FIELD32(18, 0x00040000) /* UART2 RX buffer error. */
259 #define CSR7_TIMER_CSR3_EXPIRE FIELD32(19, 0x00080000) /* TIMECSR3 timer expired (802.1H quiet period). */
260 
261 /*
262  * CSR8: Interrupt mask register.
263  * Write 1 to mask interrupt.
264  */
265 #define CSR8_TBCN_EXPIRE FIELD32(0, 0x00000001) /* beacon timer expired interrupt. */
266 #define CSR8_TWAKE_EXPIRE FIELD32(1, 0x00000002) /* wakeup timer expired interrupt. */
267 #define CSR8_TATIMW_EXPIRE FIELD32(2, 0x00000004) /* timer of atim window expired interrupt. */
268 #define CSR8_TXDONE_TXRING FIELD32(3, 0x00000008) /* tx ring transmit done interrupt. */
269 #define CSR8_TXDONE_ATIMRING FIELD32(4, 0x00000010) /* atim ring transmit done interrupt. */
270 #define CSR8_TXDONE_PRIORING FIELD32(5, 0x00000020) /* priority ring transmit done interrupt. */
271 #define CSR8_RXDONE FIELD32(6, 0x00000040) /* receive done interrupt. */
272 #define CSR8_DECRYPTION_DONE FIELD32(7, 0x00000080) /* Decryption done interrupt. */
273 #define CSR8_ENCRYPTION_DONE FIELD32(8, 0x00000100) /* Encryption done interrupt. */
274 #define CSR8_UART1_TX_TRESHOLD FIELD32(9, 0x00000200) /* UART1 TX reaches threshold. */
275 #define CSR8_UART1_RX_TRESHOLD FIELD32(10, 0x00000400) /* UART1 RX reaches threshold. */
276 #define CSR8_UART1_IDLE_TRESHOLD FIELD32(11, 0x00000800) /* UART1 IDLE over threshold. */
277 #define CSR8_UART1_TX_BUFF_ERROR FIELD32(12, 0x00001000) /* UART1 TX buffer error. */
278 #define CSR8_UART1_RX_BUFF_ERROR FIELD32(13, 0x00002000) /* UART1 RX buffer error. */
279 #define CSR8_UART2_TX_TRESHOLD FIELD32(14, 0x00004000) /* UART2 TX reaches threshold. */
280 #define CSR8_UART2_RX_TRESHOLD FIELD32(15, 0x00008000) /* UART2 RX reaches threshold. */
281 #define CSR8_UART2_IDLE_TRESHOLD FIELD32(16, 0x00010000) /* UART2 IDLE over threshold. */
282 #define CSR8_UART2_TX_BUFF_ERROR FIELD32(17, 0x00020000) /* UART2 TX buffer error. */
283 #define CSR8_UART2_RX_BUFF_ERROR FIELD32(18, 0x00040000) /* UART2 RX buffer error. */
284 #define CSR8_TIMER_CSR3_EXPIRE FIELD32(19, 0x00080000) /* TIMECSR3 timer expired (802.1H quiet period). */
285 
286 /*
287  * CSR9: Maximum frame length register.
288  */
289 #define CSR9_MAX_FRAME_UNIT FIELD32(7, 0x00000f80) /* maximum frame length in 128b unit, default: 12. */
290 
291 /*
292  * SECCSR0: WEP control register.
293  */
294 #define SECCSR0_KICK_DECRYPT FIELD32(0, 0x00000001) /* Kick decryption engine, self-clear. */
295 #define SECCSR0_ONE_SHOT FIELD32(1, 0x00000002) /* 0: ring mode, 1: One shot only mode. */
296 #define SECCSR0_DESC_ADDRESS FIELD32(2, 0xfffffffc) /* Descriptor physical address of frame. */
297 
298 /*
299  * CSR11: Back-off control register.
300  */
301 #define CSR11_CWMIN FIELD32(0, 0x0000000f) /* CWmin. Default cwmin is 31 (2^5 - 1). */
302 #define CSR11_CWMAX FIELD32(4, 0x000000f0) /* CWmax. Default cwmax is 1023 (2^10 - 1). */
303 #define CSR11_SLOT_TIME FIELD32(8, 0x00001f00) /* slot time, default is 20us for 802.11b */
304 #define CSR11_CW_SELECT FIELD32(13, 0x00002000) /* CWmin/CWmax selection, 1: Register, 0: TXD. */
305 #define CSR11_LONG_RETRY FIELD32(16, 0x00ff0000) /* long retry count. */
306 #define CSR11_SHORT_RETRY FIELD32(24, 0xff000000) /* short retry count. */
307 
308 /*
309  * CSR12: Synchronization configuration register 0.
310  * All units in 1/16 TU.
311  */
312 #define CSR12_BEACON_INTERVAL FIELD32(0, 0x0000ffff) /* beacon interval, default is 100 TU. */
313 #define CSR12_CFPMAX_DURATION FIELD32(16, 0xffff0000) /* cfp maximum duration, default is 100 TU. */
314 
315 /*
316  * CSR13: Synchronization configuration register 1.
317  * All units in 1/16 TU.
318  */
319 #define CSR13_ATIMW_DURATION FIELD32(0, 0x0000ffff) /* atim window duration. */
320 #define CSR13_CFP_PERIOD FIELD32(16, 0x00ff0000) /* cfp period, default is 0 TU. */
321 
322 /*
323  * CSR14: Synchronization control register.
324  */
325 #define CSR14_TSF_COUNT FIELD32(0, 0x00000001) /* enable tsf auto counting. */
326 #define CSR14_TSF_SYNC FIELD32(1, 0x00000006) /* tsf sync, 0: disable, 1: infra, 2: ad-hoc mode. */
327 #define CSR14_TBCN FIELD32(3, 0x00000008) /* enable tbcn with reload value. */
328 #define CSR14_TCFP FIELD32(4, 0x00000010) /* enable tcfp & cfp / cp switching. */
329 #define CSR14_TATIMW FIELD32(5, 0x00000020) /* enable tatimw & atim window switching. */
330 #define CSR14_BEACON_GEN FIELD32(6, 0x00000040) /* enable beacon generator. */
331 #define CSR14_CFP_COUNT_PRELOAD FIELD32(8, 0x0000ff00) /* cfp count preload value. */
332 #define CSR14_TBCM_PRELOAD FIELD32(16, 0xffff0000) /* tbcn preload value in units of 64us. */
333 
334 /*
335  * CSR15: Synchronization status register.
336  */
337 #define CSR15_CFP FIELD32(0, 0x00000001) /* ASIC is in contention-free period. */
338 #define CSR15_ATIMW FIELD32(1, 0x00000002) /* ASIC is in ATIM window. */
339 #define CSR15_BEACON_SENT FIELD32(2, 0x00000004) /* Beacon is send. */
340 
341 /*
342  * CSR16: TSF timer register 0.
343  */
344 #define CSR16_LOW_TSFTIMER FIELD32(0, 0xffffffff)
345 
346 /*
347  * CSR17: TSF timer register 1.
348  */
349 #define CSR17_HIGH_TSFTIMER FIELD32(0, 0xffffffff)
350 
351 /*
352  * CSR18: IFS timer register 0.
353  */
354 #define CSR18_SIFS FIELD32(0, 0x000001ff) /* sifs, default is 10 us. */
355 #define CSR18_PIFS FIELD32(16, 0x01f00000) /* pifs, default is 30 us. */
356 
357 /*
358  * CSR19: IFS timer register 1.
359  */
360 #define CSR19_DIFS FIELD32(0, 0x0000ffff) /* difs, default is 50 us. */
361 #define CSR19_EIFS FIELD32(16, 0xffff0000) /* eifs, default is 364 us. */
362 
363 /*
364  * CSR20: Wakeup timer register.
365  */
366 #define CSR20_DELAY_AFTER_TBCN FIELD32(0, 0x0000ffff) /* delay after tbcn expired in units of 1/16 TU. */
367 #define CSR20_TBCN_BEFORE_WAKEUP FIELD32(16, 0x00ff0000) /* number of beacon before wakeup. */
368 #define CSR20_AUTOWAKE FIELD32(24, 0x01000000) /* enable auto wakeup / sleep mechanism. */
369 
370 /*
371  * CSR21: EEPROM control register.
372  */
373 #define CSR21_RELOAD FIELD32(0, 0x00000001) /* Write 1 to reload eeprom content. */
374 #define CSR21_EEPROM_DATA_CLOCK FIELD32(1, 0x00000002)
375 #define CSR21_EEPROM_CHIP_SELECT FIELD32(2, 0x00000004)
376 #define CSR21_EEPROM_DATA_IN FIELD32(3, 0x00000008)
377 #define CSR21_EEPROM_DATA_OUT FIELD32(4, 0x00000010)
378 #define CSR21_TYPE_93C46 FIELD32(5, 0x00000020) /* 1: 93c46, 0:93c66. */
379 
380 /*
381  * CSR22: CFP control register.
382  */
383 #define CSR22_CFP_DURATION_REMAIN FIELD32(0, 0x0000ffff) /* cfp duration remain, in units of TU. */
384 #define CSR22_RELOAD_CFP_DURATION FIELD32(16, 0x00010000) /* Write 1 to reload cfp duration remain. */
385 
386 /*
387  * TX / RX Registers.
388  * Some values are set in TU, whereas 1 TU == 1024 us.
389  */
390 
391 /*
392  * TXCSR0: TX Control Register.
393  */
394 #define TXCSR0_KICK_TX FIELD32(0, 0x00000001) /* kick tx ring. */
395 #define TXCSR0_KICK_ATIM FIELD32(1, 0x00000002) /* kick atim ring. */
396 #define TXCSR0_KICK_PRIO FIELD32(2, 0x00000004) /* kick priority ring. */
397 #define TXCSR0_ABORT FIELD32(3, 0x00000008) /* abort all transmit related ring operation. */
398 
399 /*
400  * TXCSR1: TX Configuration Register.
401  */
402 #define TXCSR1_ACK_TIMEOUT FIELD32(0, 0x000001ff) /* ack timeout, default = sifs + 2*slottime + acktime @ 1mbps. */
403 #define TXCSR1_ACK_CONSUME_TIME FIELD32(9, 0x0003fe00) /* ack consume time, default = sifs + acktime @ 1mbps. */
404 #define TXCSR1_TSF_OFFSET FIELD32(18, 0x00fc0000) /* insert tsf offset. */
405 #define TXCSR1_AUTORESPONDER FIELD32(24, 0x01000000) /* enable auto responder which include ack & cts. */
406 
407 /*
408  * TXCSR2: Tx descriptor configuration register.
409  */
410 #define TXCSR2_TXD_SIZE FIELD32(0, 0x000000ff) /* tx descriptor size, default is 48. */
411 #define TXCSR2_NUM_TXD FIELD32(8, 0x0000ff00) /* number of txd in ring. */
412 #define TXCSR2_NUM_ATIM FIELD32(16, 0x00ff0000) /* number of atim in ring. */
413 #define TXCSR2_NUM_PRIO FIELD32(24, 0xff000000) /* number of priority in ring. */
414 
415 /*
416  * TXCSR3: TX Ring Base address register.
417  */
418 #define TXCSR3_TX_RING_REGISTER FIELD32(0, 0xffffffff)
419 
420 /*
421  * TXCSR4: TX Atim Ring Base address register.
422  */
423 #define TXCSR4_ATIM_RING_REGISTER FIELD32(0, 0xffffffff)
424 
425 /*
426  * TXCSR5: TX Prio Ring Base address register.
427  */
428 #define TXCSR5_PRIO_RING_REGISTER FIELD32(0, 0xffffffff)
429 
430 /*
431  * TXCSR6: Beacon Base address register.
432  */
433 #define TXCSR6_BEACON_REGISTER FIELD32(0, 0xffffffff)
434 
435 /*
436  * TXCSR7: Auto responder control register.
437  */
438 #define TXCSR7_AR_POWERMANAGEMENT FIELD32(0, 0x00000001) /* auto responder power management bit. */
439 
440 /*
441  * TXCSR8: CCK Tx BBP register.
442  */
443 #define TXCSR8_CCK_SIGNAL FIELD32(0, 0x000000ff) /* BBP rate field address for CCK. */
444 #define TXCSR8_CCK_SERVICE FIELD32(8, 0x0000ff00) /* BBP service field address for CCK. */
445 #define TXCSR8_CCK_LENGTH_LOW FIELD32(16, 0x00ff0000) /* BBP length low byte address for CCK. */
446 #define TXCSR8_CCK_LENGTH_HIGH FIELD32(24, 0xff000000) /* BBP length high byte address for CCK. */
447 
448 /*
449  * TXCSR9: OFDM TX BBP registers
450  */
451 #define TXCSR9_OFDM_RATE FIELD32(0, 0x000000ff) /* BBP rate field address for OFDM. */
452 #define TXCSR9_OFDM_SERVICE FIELD32(8, 0x0000ff00) /* BBP service field address for OFDM. */
453 #define TXCSR9_OFDM_LENGTH_LOW FIELD32(16, 0x00ff0000) /* BBP length low byte address for OFDM. */
454 #define TXCSR9_OFDM_LENGTH_HIGH FIELD32(24, 0xff000000) /* BBP length high byte address for OFDM. */
455 
456 /*
457  * RXCSR0: RX Control Register.
458  */
459 #define RXCSR0_DISABLE_RX FIELD32(0, 0x00000001) /* disable rx engine. */
460 #define RXCSR0_DROP_CRC FIELD32(1, 0x00000002) /* drop crc error. */
461 #define RXCSR0_DROP_PHYSICAL FIELD32(2, 0x00000004) /* drop physical error. */
462 #define RXCSR0_DROP_CONTROL FIELD32(3, 0x00000008) /* drop control frame. */
463 #define RXCSR0_DROP_NOT_TO_ME FIELD32(4, 0x00000010) /* drop not to me unicast frame. */
464 #define RXCSR0_DROP_TODS FIELD32(5, 0x00000020) /* drop frame tods bit is true. */
465 #define RXCSR0_DROP_VERSION_ERROR FIELD32(6, 0x00000040) /* drop version error frame. */
466 #define RXCSR0_PASS_CRC FIELD32(7, 0x00000080) /* pass all packets with crc attached. */
467 #define RXCSR0_PASS_PLCP FIELD32(8, 0x00000100) /* Pass all packets with 4 bytes PLCP attached. */
468 #define RXCSR0_DROP_MCAST FIELD32(9, 0x00000200) /* Drop multicast frames. */
469 #define RXCSR0_DROP_BCAST FIELD32(10, 0x00000400) /* Drop broadcast frames. */
470 #define RXCSR0_ENABLE_QOS FIELD32(11, 0x00000800) /* Accept QOS data frame and parse QOS field. */
471 
472 /*
473  * RXCSR1: RX descriptor configuration register.
474  */
475 #define RXCSR1_RXD_SIZE FIELD32(0, 0x000000ff) /* rx descriptor size, default is 32b. */
476 #define RXCSR1_NUM_RXD FIELD32(8, 0x0000ff00) /* number of rxd in ring. */
477 
478 /*
479  * RXCSR2: RX Ring base address register.
480  */
481 #define RXCSR2_RX_RING_REGISTER FIELD32(0, 0xffffffff)
482 
483 /*
484  * RXCSR3: BBP ID register for Rx operation.
485  */
486 #define RXCSR3_BBP_ID0 FIELD32(0, 0x0000007f) /* bbp register 0 id. */
487 #define RXCSR3_BBP_ID0_VALID FIELD32(7, 0x00000080) /* bbp register 0 id is valid or not. */
488 #define RXCSR3_BBP_ID1 FIELD32(8, 0x00007f00) /* bbp register 1 id. */
489 #define RXCSR3_BBP_ID1_VALID FIELD32(15, 0x00008000) /* bbp register 1 id is valid or not. */
490 #define RXCSR3_BBP_ID2 FIELD32(16, 0x007f0000) /* bbp register 2 id. */
491 #define RXCSR3_BBP_ID2_VALID FIELD32(23, 0x00800000) /* bbp register 2 id is valid or not. */
492 #define RXCSR3_BBP_ID3 FIELD32(24, 0x7f000000) /* bbp register 3 id. */
493 #define RXCSR3_BBP_ID3_VALID FIELD32(31, 0x80000000) /* bbp register 3 id is valid or not. */
494 
495 /*
496  * ARCSR1: Auto Responder PLCP config register 1.
497  */
498 #define ARCSR1_AR_BBP_DATA2 FIELD32(0, 0x000000ff) /* Auto responder BBP register 2 data. */
499 #define ARCSR1_AR_BBP_ID2 FIELD32(8, 0x0000ff00) /* Auto responder BBP register 2 Id. */
500 #define ARCSR1_AR_BBP_DATA3 FIELD32(16, 0x00ff0000) /* Auto responder BBP register 3 data. */
501 #define ARCSR1_AR_BBP_ID3 FIELD32(24, 0xff000000) /* Auto responder BBP register 3 Id. */
502 
503 /*
504  * Miscellaneous Registers.
505  * Some values are set in TU, whereas 1 TU == 1024 us.
506  */
507 
508 /*
509  * PCISR: PCI control register.
510  */
511 #define PCICSR_BIG_ENDIAN FIELD32(0, 0x00000001) /* 1: big endian, 0: little endian. */
512 #define PCICSR_RX_TRESHOLD FIELD32(1, 0x00000006) /* rx threshold in dw to start pci access */
513  /* 0: 16dw (default), 1: 8dw, 2: 4dw, 3: 32dw. */
514 #define PCICSR_TX_TRESHOLD FIELD32(3, 0x00000018) /* tx threshold in dw to start pci access */
515  /* 0: 0dw (default), 1: 1dw, 2: 4dw, 3: forward. */
516 #define PCICSR_BURST_LENTH FIELD32(5, 0x00000060) /* pci burst length */
517  /* 0: 4dw (default, 1: 8dw, 2: 16dw, 3:32dw. */
518 #define PCICSR_ENABLE_CLK FIELD32(7, 0x00000080) /* enable clk_run, */
519  /* pci clock can't going down to non-operational. */
520 #define PCICSR_READ_MULTIPLE FIELD32(8, 0x00000100) /* Enable memory read multiple. */
521 #define PCICSR_WRITE_INVALID FIELD32(9, 0x00000200) /* Enable memory write & invalid. */
522 
523 /*
524  * PWRCSR1: Manual power control / status register.
525  * state: 0 deep_sleep, 1: sleep, 2: standby, 3: awake.
526  */
527 #define PWRCSR1_SET_STATE FIELD32(0, 0x00000001) /* set state. Write 1 to trigger, self cleared. */
528 #define PWRCSR1_BBP_DESIRE_STATE FIELD32(1, 0x00000006) /* BBP desired state. */
529 #define PWRCSR1_RF_DESIRE_STATE FIELD32(3, 0x00000018) /* RF desired state. */
530 #define PWRCSR1_BBP_CURR_STATE FIELD32(5, 0x00000060) /* BBP current state. */
531 #define PWRCSR1_RF_CURR_STATE FIELD32(7, 0x00000180) /* RF current state. */
532 #define PWRCSR1_PUT_TO_SLEEP FIELD32(9, 0x00000200) /* put to sleep. Write 1 to trigger, self cleared. */
533 
534 /*
535  * TIMECSR: Timer control register.
536  */
537 #define TIMECSR_US_COUNT FIELD32(0, 0x000000ff) /* 1 us timer count in units of clock cycles. */
538 #define TIMECSR_US_64_COUNT FIELD32(8, 0x0000ff00) /* 64 us timer count in units of 1 us timer. */
539 #define TIMECSR_BEACON_EXPECT FIELD32(16, 0x00070000) /* Beacon expect window. */
540 
541 /*
542  * MACCSR1: MAC configuration register 1.
543  */
544 #define MACCSR1_KICK_RX FIELD32(0, 0x00000001) /* kick one-shot rx in one-shot rx mode. */
545 #define MACCSR1_ONESHOT_RXMODE FIELD32(1, 0x00000002) /* enable one-shot rx mode for debugging. */
546 #define MACCSR1_BBPRX_RESET_MODE FIELD32(2, 0x00000004) /* ralink bbp rx reset mode. */
547 #define MACCSR1_AUTO_TXBBP FIELD32(3, 0x00000008) /* auto tx logic access bbp control register. */
548 #define MACCSR1_AUTO_RXBBP FIELD32(4, 0x00000010) /* auto rx logic access bbp control register. */
549 #define MACCSR1_LOOPBACK FIELD32(5, 0x00000060) /* loopback mode. */
550  /* 0: normal, 1: internal, 2: external, 3:rsvd. */
551 #define MACCSR1_INTERSIL_IF FIELD32(7, 0x00000080) /* intersil if calibration pin. */
552 
553 /*
554  * RALINKCSR: Ralink Rx auto-reset BBCR.
555  */
556 #define RALINKCSR_AR_BBP_DATA0 FIELD32(0, 0x000000ff) /* auto reset bbp register 0 data. */
557 #define RALINKCSR_AR_BBP_ID0 FIELD32(8, 0x00007f00) /* auto reset bbp register 0 id. */
558 #define RALINKCSR_AR_BBP_VALID0 FIELD32(15, 0x00008000) /* auto reset bbp register 0 valid. */
559 #define RALINKCSR_AR_BBP_DATA1 FIELD32(16, 0x00ff0000) /* auto reset bbp register 1 data. */
560 #define RALINKCSR_AR_BBP_ID1 FIELD32(24, 0x7f000000) /* auto reset bbp register 1 id. */
561 #define RALINKCSR_AR_BBP_VALID1 FIELD32(31, 0x80000000) /* auto reset bbp register 1 valid. */
562 
563 /*
564  * BCNCSR: Beacon interval control register.
565  */
566 #define BCNCSR_CHANGE FIELD32(0, 0x00000001) /* write one to change beacon interval. */
567 #define BCNCSR_DELTATIME FIELD32(1, 0x0000001e) /* the delta time value. */
568 #define BCNCSR_NUM_BEACON FIELD32(5, 0x00001fe0) /* number of beacon according to mode. */
569 #define BCNCSR_MODE FIELD32(13, 0x00006000) /* please refer to asic specs. */
570 #define BCNCSR_PLUS FIELD32(15, 0x00008000) /* plus or minus delta time value. */
571 
572 /*
573  * BBPCSR: BBP serial control register.
574  */
575 #define BBPCSR_VALUE FIELD32(0, 0x000000ff) /* register value to program into bbp. */
576 #define BBPCSR_REGNUM FIELD32(8, 0x00007f00) /* selected bbp register. */
577 #define BBPCSR_BUSY FIELD32(15, 0x00008000) /* 1: asic is busy execute bbp programming. */
578 #define BBPCSR_WRITE_CONTROL FIELD32(16, 0x00010000) /* 1: write bbp, 0: read bbp. */
579 
580 /*
581  * RFCSR: RF serial control register.
582  */
583 #define RFCSR_VALUE FIELD32(0, 0x00ffffff) /* register value + id to program into rf/if. */
584 #define RFCSR_NUMBER_OF_BITS FIELD32(24, 0x1f000000) /* number of bits used in value (i:20, rfmd:22). */
585 #define RFCSR_IF_SELECT FIELD32(29, 0x20000000) /* chip to program: 0: rf, 1: if. */
586 #define RFCSR_PLL_LD FIELD32(30, 0x40000000) /* rf pll_ld status. */
587 #define RFCSR_BUSY FIELD32(31, 0x80000000) /* 1: asic is busy execute rf programming. */
588 
589 /*
590  * LEDCSR: LED control register.
591  */
592 #define LEDCSR_ON_PERIOD FIELD32(0, 0x000000ff) /* on period, default 70ms. */
593 #define LEDCSR_OFF_PERIOD FIELD32(8, 0x0000ff00) /* off period, default 30ms. */
594 #define LEDCSR_LINK FIELD32(16, 0x00010000) /* 0: linkoff, 1: linkup. */
595 #define LEDCSR_ACTIVITY FIELD32(17, 0x00020000) /* 0: idle, 1: active. */
596 #define LEDCSR_LINK_POLARITY FIELD32(18, 0x00040000) /* 0: active low, 1: active high. */
597 #define LEDCSR_ACTIVITY_POLARITY FIELD32(19, 0x00080000) /* 0: active low, 1: active high. */
598 #define LEDCSR_LED_DEFAULT FIELD32(20, 0x00100000) /* LED state for "enable" 0: ON, 1: OFF. */
599 
600 /*
601  * GPIOCSR: GPIO control register.
602  */
603 #define GPIOCSR_BIT0 FIELD32(0, 0x00000001)
604 #define GPIOCSR_BIT1 FIELD32(1, 0x00000002)
605 #define GPIOCSR_BIT2 FIELD32(2, 0x00000004)
606 #define GPIOCSR_BIT3 FIELD32(3, 0x00000008)
607 #define GPIOCSR_BIT4 FIELD32(4, 0x00000010)
608 #define GPIOCSR_BIT5 FIELD32(5, 0x00000020)
609 #define GPIOCSR_BIT6 FIELD32(6, 0x00000040)
610 #define GPIOCSR_BIT7 FIELD32(7, 0x00000080)
611 #define GPIOCSR_DIR0 FIELD32(8, 0x00000100)
612 #define GPIOCSR_DIR1 FIELD32(9, 0x00000200)
613 #define GPIOCSR_DIR2 FIELD32(10, 0x00000400)
614 #define GPIOCSR_DIR3 FIELD32(11, 0x00000800)
615 #define GPIOCSR_DIR4 FIELD32(12, 0x00001000)
616 #define GPIOCSR_DIR5 FIELD32(13, 0x00002000)
617 #define GPIOCSR_DIR6 FIELD32(14, 0x00004000)
618 #define GPIOCSR_DIR7 FIELD32(15, 0x00008000)
619 
620 /*
621  * BCNCSR1: Tx BEACON offset time control register.
622  */
623 #define BCNCSR1_PRELOAD FIELD32(0, 0x0000ffff) /* beacon timer offset in units of usec. */
624 #define BCNCSR1_BEACON_CWMIN FIELD32(16, 0x000f0000) /* 2^CwMin. */
625 
626 /*
627  * MACCSR2: TX_PE to RX_PE turn-around time control register
628  */
629 #define MACCSR2_DELAY FIELD32(0, 0x000000ff) /* RX_PE low width, in units of pci clock cycle. */
630 
631 /*
632  * SECCSR1_RT2509: WEP control register
633  */
634 #define SECCSR1_KICK_ENCRYPT FIELD32(0, 0x00000001) /* Kick encryption engine, self-clear. */
635 #define SECCSR1_ONE_SHOT FIELD32(1, 0x00000002) /* 0: ring mode, 1: One shot only mode. */
636 #define SECCSR1_DESC_ADDRESS FIELD32(2, 0xfffffffc) /* Descriptor physical address of frame. */
637 
638 /*
639  * RF registers
640  */
641 #define RF1_TUNER FIELD32(17, 0x00020000)
642 #define RF3_TUNER FIELD32(8, 0x00000100)
643 #define RF3_TXPOWER FIELD32(9, 0x00003e00)
644 
645 /*
646  * EEPROM content format.
647  * The wordsize of the EEPROM is 16 bits.
648  */
649 
650 /*
651  * EEPROM operation defines.
652  */
653 #define EEPROM_WIDTH_93c46 6
654 #define EEPROM_WIDTH_93c66 8
655 #define EEPROM_WRITE_OPCODE 0x05
656 #define EEPROM_READ_OPCODE 0x06
657 
658 /*
659  * EEPROM antenna.
660  */
661 #define EEPROM_ANTENNA_NUM FIELD16(0, 0x0003) /* Number of antenna's. */
662 #define EEPROM_ANTENNA_TX_DEFAULT FIELD16(2, 0x000c) /* Default antenna 0: diversity, 1: A, 2: B. */
663 #define EEPROM_ANTENNA_RX_DEFAULT FIELD16(4, 0x0030) /* Default antenna 0: diversity, 1: A, 2: B. */
664 #define EEPROM_ANTENNA_LED_MODE FIELD16(6, 0x01c0) /* 0: default, 1: TX/RX activity, */
665  /* 2: Single LED (ignore link), 3: reserved. */
666 #define EEPROM_ANTENNA_DYN_TXAGC FIELD16(9, 0x0200) /* Dynamic TX AGC control. */
667 #define EEPROM_ANTENNA_HARDWARE_RADIO FIELD16(10, 0x0400) /* 1: Hardware controlled radio. Read GPIO0. */
668 #define EEPROM_ANTENNA_RF_TYPE FIELD16(11, 0xf800) /* rf_type of this adapter. */
669 
670 /*
671  * EEPROM geography.
672  */
673 #define EEPROM_GEOGRAPHY_GEO FIELD16(8, 0x0f00) /* Default geography setting for device. */
674 
675 /*
676  * EEPROM NIC config.
677  */
678 #define EEPROM_NIC_CARDBUS_ACCEL FIELD16(0, 0x0001) /* 0: enable, 1: disable. */
679 #define EEPROM_NIC_DYN_BBP_TUNE FIELD16(1, 0x0002) /* 0: enable, 1: disable. */
680 #define EEPROM_NIC_CCK_TX_POWER FIELD16(2, 0x000c) /* CCK TX power compensation. */
681 
682 /*
683  * EEPROM TX power.
684  */
685 #define EEPROM_TX_POWER1 FIELD16(0, 0x00ff)
686 #define EEPROM_TX_POWER2 FIELD16(8, 0xff00)
687 
688 /*
689  * EEPROM BBP.
690  */
691 #define EEPROM_BBP_VALUE FIELD16(0, 0x00ff)
692 #define EEPROM_BBP_REG_ID FIELD16(8, 0xff00)
693 
694 /*
695  * EEPROM VERSION.
696  */
697 #define EEPROM_VERSION_FAE FIELD16(0, 0x00ff) /* FAE release number. */
698 #define EEPROM_VERSION FIELD16(8, 0xff00)
699 
700 /*
701  * DMA ring defines and data structures.
702  */
703 
704 /*
705  * Size of a single descriptor.
706  */
707 #define SIZE_DESCRIPTOR 48
708 
709 /*
710  * TX descriptor format for TX, PRIO, ATIM and Beacon Ring.
711  */
712 struct _txd{
713  u32 word0;
714 #define TXD_W0_OWNER_NIC FIELD32(0, 0x00000001)
715 #define TXD_W0_VALID FIELD32(1, 0x00000002)
716 #define TXD_W0_RESULT FIELD32(2, 0x0000001c) /* Set by device. */
717 #define TXD_W0_RETRY_COUNT FIELD32(5, 0x000000e0) /* Set by device. */
718 #define TXD_W0_MORE_FRAG FIELD32(8, 0x00000100) /* Set by device. */
719 #define TXD_W0_ACK FIELD32(9, 0x00000200)
720 #define TXD_W0_TIMESTAMP FIELD32(10, 0x00000400)
721 #define TXD_W0_OFDM FIELD32(11, 0x00000800)
722 #define TXD_W0_CIPHER_OWNER FIELD32(12, 0x00001000)
723 #define TXD_W0_IFS FIELD32(13, 0x00006000)
724 #define TXD_W0_RETRY_MODE FIELD32(15, 0x00008000)
725 #define TXD_W0_DATABYTE_COUNT FIELD32(16, 0x0fff0000)
726 #define TXD_W0_CIPHER_ALG FIELD32(29, 0xe0000000)
727 
728  u32 word1;
729 #define TXD_W1_BUFFER_ADDRESS FIELD32(0, 0xffffffff)
730 
731  u32 word2;
732 #define TXD_W2_IV_OFFSET FIELD32(0, 0x0000003f)
733 #define TXD_W2_AIFS FIELD32(6, 0x000000c0)
734 #define TXD_W2_CWMIN FIELD32(8, 0x00000f00)
735 #define TXD_W2_CWMAX FIELD32(12, 0x0000f000)
736 
737  u32 word3;
738 #define TXD_W3_PLCP_SIGNAL FIELD32(0, 0x000000ff)
739 #define TXD_W3_PLCP_SERVICE FIELD32(8, 0x0000ff00)
740 #define TXD_W3_PLCP_LENGTH_LOW FIELD32(16, 0x00ff0000)
741 #define TXD_W3_PLCP_LENGTH_HIGH FIELD32(24, 0xff000000)
742 
743  u32 word4;
744 #define TXD_W4_IV FIELD32(0, 0xffffffff)
745 
746  u32 word5;
747 #define TXD_W5_EIV FIELD32(0, 0xffffffff)
748 
749  u32 word6;
750 #define TXD_W6_KEY FIELD32(0, 0xffffffff)
751 
752  u32 word7;
753 #define TXD_W7_KEY FIELD32(0, 0xffffffff)
754 
755  u32 word8;
756 #define TXD_W8_KEY FIELD32(0, 0xffffffff)
757 
758  u32 word9;
759 #define TXD_W9_KEY FIELD32(0, 0xffffffff)
760 
761  u32 word10;
762 #define TXD_W10_RTS FIELD32(0, 0x00000001)
763 #define TXD_W10_TX_RATE FIELD32(0, 0x000000fe) /* For module only. */
764 } __attribute__ ((packed));
765 
766 /*
767  * RX descriptor format for RX Ring.
768  */
769 struct _rxd{
770  u32 word0;
771 #define RXD_W0_OWNER_NIC FIELD32(0, 0x00000001)
772 #define RXD_W0_UNICAST_TO_ME FIELD32(1, 0x00000002)
773 #define RXD_W0_MULTICAST FIELD32(2, 0x00000004)
774 #define RXD_W0_BROADCAST FIELD32(3, 0x00000008)
775 #define RXD_W0_MY_BSS FIELD32(4, 0x00000010)
776 #define RXD_W0_CRC FIELD32(5, 0x00000020)
777 #define RXD_W0_OFDM FIELD32(6, 0x00000040)
778 #define RXD_W0_PHYSICAL_ERROR FIELD32(7, 0x00000080)
779 #define RXD_W0_CIPHER_OWNER FIELD32(8, 0x00000100)
780 #define RXD_W0_ICV_ERROR FIELD32(9, 0x00000200)
781 #define RXD_W0_IV_OFFSET FIELD32(10, 0x0000fc00)
782 #define RXD_W0_DATABYTE_COUNT FIELD32(16, 0x0fff0000)
783 #define RXD_W0_CIPHER_ALG FIELD32(29, 0xe0000000)
784 
785  u32 word1;
786 #define RXD_W1_BUFFER_ADDRESS FIELD32(0, 0xffffffff)
787 
788  u32 word2;
789 #define RXD_W2_BBR0 FIELD32(0, 0x000000ff)
790 #define RXD_W2_RSSI FIELD32(8, 0x0000ff00)
791 #define RXD_W2_TA FIELD32(16, 0xffff0000)
792 
793  u32 word3;
794 #define RXD_W3_TA FIELD32(0, 0xffffffff)
795 
796  u32 word4;
797 #define RXD_W4_IV FIELD32(0, 0xffffffff)
798 
799  u32 word5;
800 #define RXD_W5_EIV FIELD32(0, 0xffffffff)
801 
802  u32 word6;
803 #define RXD_W6_KEY FIELD32(0, 0xffffffff)
804 
805  u32 word7;
806 #define RXD_W7_KEY FIELD32(0, 0xffffffff)
807 
808  u32 word8;
809 #define RXD_W8_KEY FIELD32(0, 0xffffffff)
810 
811  u32 word9;
812 #define RXD_W9_KEY FIELD32(0, 0xffffffff)
813 
814  u32 word10;
815 #define RXD_W10_DROP FIELD32(0, 0x00000001)
816 } __attribute__ ((packed));
817 
818 
819 /*
820  * _rt2x00_pci
821  * This is the main structure which contains all variables required to communicate with the PCI device.
822  */
823 struct _rt2x00_pci{
824 
825  /*
826  * PCI device structure.
827  */
828  struct pci_dev *pci_dev;
829 
830  /*
831  * Chipset identification.
832  */
833  struct _rt2x00_chip chip;
834 
835  /*
836  * csr_addr
837  * Base address of device registers, all exact register addresses are calculated from this address.
838  */
839  void __iomem *csr_addr;
840 
841  /*
842  * RF register values for current channel.
843  */
844  struct _rf_channel channel;
845 
846  /*
847  * EEPROM bus width.
848  */
849  u8 eeprom_width;
850 
851  u8 __pad; /* For alignment only. */
852 
853  /*
854  * EEPROM BBP data.
855  */
856  u16 eeprom[EEPROM_BBP_SIZE];
857 
858  /*
859  * DMA packet ring.
860  */
861  struct _data_ring rx;
862  struct _data_ring tx;
863 
864  rtdm_irq_t irq_handle;
865  rtdm_lock_t lock;
866 
867 } __attribute__ ((packed));
868 
869 static int rt2x00_get_rf_value(const struct _rt2x00_chip *chip, const u8 channel, struct _rf_channel *rf_reg) {
870 
871  int index = 0x00;
872 
873  index = rt2x00_get_channel_index(channel);
874  if(index < 0)
875  return -EINVAL;
876 
877  memset(rf_reg, 0x00, sizeof(*rf_reg));
878 
879  if(rt2x00_rf(chip, RF2522)){
880  rf_reg->rf1 = 0x00002050;
881  rf_reg->rf3 = 0x00000101;
882  goto update_rf2_1;
883  }
884  if(rt2x00_rf(chip, RF2523)){
885  rf_reg->rf1 = 0x00022010;
886  rf_reg->rf3 = 0x000e0111;
887  rf_reg->rf4 = 0x00000a1b;
888  goto update_rf2_2;
889  }
890  if(rt2x00_rf(chip, RF2524)){
891  rf_reg->rf1 = 0x00032020;
892  rf_reg->rf3 = 0x00000101;
893  rf_reg->rf4 = 0x00000a1b;
894  goto update_rf2_2;
895  }
896  if(rt2x00_rf(chip, RF2525)){
897  rf_reg->rf1 = 0x00022020;
898  rf_reg->rf2 = 0x00080000;
899  rf_reg->rf3 = 0x00060111;
900  rf_reg->rf4 = 0x00000a1b;
901  goto update_rf2_2;
902  }
903  if(rt2x00_rf(chip, RF2525E)){
904  rf_reg->rf2 = 0x00080000;
905  rf_reg->rf3 = 0x00060111;
906  goto update_rf2_3;
907  }
908  if(rt2x00_rf(chip, RF5222)){
909  rf_reg->rf3 = 0x00000101;
910  goto update_rf2_3;
911  }
912 
913  return -EINVAL;
914 
915  update_rf2_1: /* RF2522. */
916  rf_reg->rf2 = 0x000c1fda + (index * 0x14);
917  if(channel == 14)
918  rf_reg->rf2 += 0x0000001c;
919  goto exit;
920 
921  update_rf2_2: /* RF2523, RF2524, RF2525. */
922  rf_reg->rf2 |= 0x00000c9e + (index * 0x04);
923  if(rf_reg->rf2 & 0x00000040)
924  rf_reg->rf2 += 0x00000040;
925  if(channel == 14){
926  rf_reg->rf2 += 0x08;
927  rf_reg->rf4 &= ~0x00000018;
928  }
929  goto exit;
930 
931  update_rf2_3: /* RF2525E, RF5222. */
932  if(OFDM_CHANNEL(channel)){
933  rf_reg->rf1 = 0x00022020;
934  rf_reg->rf2 |= 0x00001136 + (index * 0x04);
935  if(rf_reg->rf2 & 0x00000040)
936  rf_reg->rf2 += 0x00000040;
937  if(channel == 14){
938  rf_reg->rf2 += 0x04;
939  rf_reg->rf4 = 0x00000a1b;
940  }else{
941  rf_reg->rf4 = 0x00000a0b;
942  }
943  }
944  else if(UNII_LOW_CHANNEL(channel)){
945  rf_reg->rf1 = 0x00022010;
946  rf_reg->rf2 = 0x00018896 + (index * 0x04);
947  rf_reg->rf4 = 0x00000a1f;
948  }
949  else if(HIPERLAN2_CHANNEL(channel)){
950  rf_reg->rf1 = 0x00022010;
951  rf_reg->rf2 = 0x00008802 + (index * 0x04);
952  rf_reg->rf4 = 0x00000a0f;
953  }
954  else if(UNII_HIGH_CHANNEL(channel)){
955  rf_reg->rf1 = 0x00022020;
956  rf_reg->rf2 = 0x000090a6 + (index * 0x08);
957  rf_reg->rf4 = 0x00000a07;
958  }
959 
960  exit:
961  rf_reg->rf1 = cpu_to_le32(rf_reg->rf1);
962  rf_reg->rf2 = cpu_to_le32(rf_reg->rf2);
963  rf_reg->rf3 = cpu_to_le32(rf_reg->rf3);
964  rf_reg->rf4 = cpu_to_le32(rf_reg->rf4);
965 
966  return 0;
967 }
968 
969 /*
970  * Get txpower value in dBm mathing the requested percentage.
971  */
972 static inline u8
973 rt2x00_get_txpower(const struct _rt2x00_chip *chip, const u8 tx_power) {
974 
975  return tx_power / 100 * 31;
976 
977  /*
978  if(tx_power <= 3)
979  return 19;
980  else if(tx_power <= 12)
981  return 22;
982  else if(tx_power <= 25)
983  return 25;
984  else if(tx_power <= 50)
985  return 28;
986  else if(tx_power <= 75)
987  return 30;
988  else if(tx_power <= 100)
989  return 31;
990 
991  ERROR("Invalid tx_power.\n");
992  return 31;
993  */
994 }
995 
996 /*
997  * Ring handlers.
998  */
999 static inline int rt2x00_pci_alloc_ring(
1000  struct _rt2x00_core *core,
1001  struct _data_ring *ring,
1002  const u8 ring_type,
1003  const u16 max_entries,
1004  const u16 entry_size,
1005  const u16 desc_size) {
1006 
1007  struct _rt2x00_pci *rt2x00pci = rt2x00_priv(core);
1008 
1009  rt2x00_init_ring(core, ring, ring_type, max_entries, entry_size, desc_size);
1010 
1011  ring->data_addr = dma_alloc_coherent(&rt2x00pci->pci_dev->dev, ring->mem_size, &ring->data_dma, GFP_KERNEL);
1012  if(!ring->data_addr)
1013  return -ENOMEM;
1014 
1015  memset(ring->data_addr, 0x00, ring->mem_size);
1016 
1017  return 0;
1018 }
1019 
1020 static int
1021 rt2x00_pci_alloc_rings(struct _rt2x00_core *core) {
1022 
1023  struct _rt2x00_pci *rt2x00pci = rt2x00_priv(core);
1024 
1025  if(rt2x00_pci_alloc_ring(core, &rt2x00pci->rx, RING_RX, RX_ENTRIES, DATA_FRAME_SIZE, SIZE_DESCRIPTOR)
1026  || rt2x00_pci_alloc_ring(core, &rt2x00pci->tx, RING_TX, TX_ENTRIES, DATA_FRAME_SIZE, SIZE_DESCRIPTOR)) {
1027  ERROR("DMA allocation failed.\n");
1028  return -ENOMEM;
1029  }
1030 
1031  return 0;
1032 }
1033 
1034 static inline void
1035 rt2x00_pci_free_ring(struct _data_ring *ring) {
1036 
1037  struct _rt2x00_pci *rt2x00pci = rt2x00_priv(ring->core);
1038 
1039  if(ring->data_addr)
1040  dma_free_coherent(&rt2x00pci->pci_dev->dev, ring->mem_size, ring->data_addr, ring->data_dma);
1041  ring->data_addr = NULL;
1042 
1043  rt2x00_deinit_ring(ring);
1044 }
1045 
1046 static void
1047 rt2x00_pci_free_rings(struct _rt2x00_core *core) {
1048 
1049  struct _rt2x00_pci *rt2x00pci = rt2x00_priv(core);
1050 
1051  rt2x00_pci_free_ring(&rt2x00pci->rx);
1052  rt2x00_pci_free_ring(&rt2x00pci->tx);
1053 }
1054 
1055 /*
1056  * Macro's for calculating exact position in data ring.
1057  */
1058 #define DESC_BASE(__ring) ( (void*)((__ring)->data_addr) )
1059 #define DATA_BASE(__ring) ( (void*)(DESC_BASE(__ring) + ((__ring)->max_entries * (__ring)->desc_size)) )
1060 
1061 #define __DESC_ADDR(__ring, __index) ( (void*)(DESC_BASE(__ring) + ((__index) * (__ring)->desc_size)) )
1062 #define __DATA_ADDR(__ring, __index) ( (void*)(DATA_BASE(__ring) + ((__index) * (__ring)->entry_size)) )
1063 
1064 #define DESC_ADDR(__ring) ( __DESC_ADDR(__ring, (__ring)->index) )
1065 #define DESC_ADDR_DONE(__ring) ( __DESC_ADDR(__ring, (__ring)->index_done) )
1066 
1067 #define DATA_ADDR(__ring) ( __DATA_ADDR(__ring, (__ring)->index) )
1068 #define DATA_ADDR_DONE(__ring) ( __DATA_ADDR(__ring, (__ring)->index_done) )
1069 
1070 /*
1071  * Register access.
1072  * All access to the registers will go through rt2x00_register_read and rt2x00_register_write.
1073  * BBP and RF register require indirect register access through the register BBPCSR and RFCSR.
1074  * The indirect register access work with busy bits, and a read or write function call can fail.
1075  * Specific fields within a register can be accessed using the set and get field routines,
1076  * these function will handle the requirement of little_endian and big_endian conversions.
1077  */
1078 #define REGISTER_BUSY_COUNT 10 /* Number of retries before failing access BBP & RF indirect register */
1079 #define REGISTER_BUSY_DELAY 100 /* Delay between each register access retry. (us) */
1080 
1081 static void
1082 rt2x00_register_read(const struct _rt2x00_pci *rt2x00pci, const unsigned long offset, u32 *value) {
1083 
1084  *value = readl((void*)(rt2x00pci->csr_addr + offset));
1085 }
1086 
1087 static void
1088 rt2x00_register_multiread(const struct _rt2x00_pci *rt2x00pci, const unsigned long offset, u32 *value, const u16 length) {
1089 
1090  memcpy_fromio((void*)value, (void*)(rt2x00pci->csr_addr + offset), length);
1091 }
1092 
1093 static void
1094 rt2x00_register_write(const struct _rt2x00_pci *rt2x00pci, const unsigned long offset, const u32 value) {
1095 
1096  writel(value, (void*)(rt2x00pci->csr_addr + offset));
1097 }
1098 
1099 static void
1100 rt2x00_register_multiwrite(const struct _rt2x00_pci *rt2x00pci, const unsigned long offset, u32 *value, const u16 length) {
1101 
1102  memcpy_toio((void*)(rt2x00pci->csr_addr + offset), (void*)value, length);
1103 }
1104 
1105 static void
1106 rt2x00_bbp_regwrite(const struct _rt2x00_pci *rt2x00pci, const u8 reg_id, const u8 value) {
1107 
1108  u32 reg = 0x00000000;
1109  u8 counter = 0x00;
1110 
1111  for(counter = 0x00; counter < REGISTER_BUSY_COUNT; counter++){
1112  rt2x00_register_read(rt2x00pci, BBPCSR, &reg);
1113  if(!rt2x00_get_field32(reg, BBPCSR_BUSY))
1114  goto bbp_write;
1115  udelay(REGISTER_BUSY_DELAY);
1116  }
1117 
1118  ERROR("BBPCSR register busy. Write failed\n");
1119  return;
1120 
1121  bbp_write:
1122  reg = 0x00000000;
1123  rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
1124  rt2x00_set_field32(&reg, BBPCSR_REGNUM, reg_id);
1125  rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
1126  rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
1127 
1128  rt2x00_register_write(rt2x00pci, BBPCSR, reg);
1129 }
1130 
1131 static void
1132 rt2x00_bbp_regread(const struct _rt2x00_pci *rt2x00pci, const u8 reg_id, u8 *value) {
1133 
1134  u32 reg = 0x00000000;
1135  u8 counter = 0x00;
1136 
1137  /*
1138  * We first have to acquire the requested BBP register,
1139  * so we write the register id into the BBP register first.
1140  */
1141  rt2x00_set_field32(&reg, BBPCSR_REGNUM, reg_id);
1142  rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
1143  rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
1144 
1145  rt2x00_register_write(rt2x00pci, BBPCSR, reg);
1146 
1147  for(counter = 0x00; counter < REGISTER_BUSY_COUNT; counter++){
1148  rt2x00_register_read(rt2x00pci, BBPCSR, &reg);
1149  if(!rt2x00_get_field32(reg, BBPCSR_BUSY)){
1150  *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
1151  return;
1152  }
1153  udelay(REGISTER_BUSY_DELAY);
1154  }
1155 
1156  ERROR("BBPCSR register busy. Read failed\n");
1157  *value = 0xff;
1158 }
1159 
1160 static void rt2x00_rf_regwrite(const struct _rt2x00_pci *rt2x00pci, const u32 value) {
1161 
1162  u32 reg = 0x00000000;
1163  u8 counter = 0x00;
1164 
1165  for(counter = 0x00; counter < REGISTER_BUSY_COUNT; counter++){
1166  rt2x00_register_read(rt2x00pci, RFCSR, &reg);
1167  if(!rt2x00_get_field32(reg, RFCSR_BUSY))
1168  goto rf_write;
1169  udelay(REGISTER_BUSY_DELAY);
1170  }
1171 
1172  ERROR("RFCSR register busy. Write failed\n");
1173  return;
1174 
1175  rf_write:
1176  reg = value;
1177  rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
1178  rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
1179  rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
1180 
1181  // printk(KERN_INFO "DEBUG: %s:%d: reg=%x\n", __FILE__, __LINE__, reg);
1182 
1183  rt2x00_register_write(rt2x00pci, RFCSR, reg);
1184 }
1185 
1186 /*
1187  * EEPROM access.
1188  * The EEPROM is being accessed by word index.
1189  * rt2x00_eeprom_read_word is the main access function that can be called by
1190  * the rest of the module. It will take the index number of the eeprom word
1191  * and the bus width.
1192  */
1193 static inline void
1194 rt2x00_eeprom_pulse_high(const struct _rt2x00_pci *rt2x00pci, u32 *flags) {
1195 
1196  rt2x00_set_field32(flags, CSR21_EEPROM_DATA_CLOCK, 1);
1197  rt2x00_register_write(rt2x00pci, CSR21, *flags);
1198  udelay(1);
1199 }
1200 
1201 static inline void
1202 rt2x00_eeprom_pulse_low(const struct _rt2x00_pci *rt2x00pci, u32 *flags) {
1203 
1204  rt2x00_set_field32(flags, CSR21_EEPROM_DATA_CLOCK, 0);
1205  rt2x00_register_write(rt2x00pci, CSR21, *flags);
1206  udelay(1);
1207 }
1208 
1209 static void
1210 rt2x00_eeprom_shift_out_bits(const struct _rt2x00_pci *rt2x00pci, const u16 data, const u16 count) {
1211 
1212  u32 flags = 0x00000000;
1213  u32 mask = 0x0001 << (count - 1);
1214 
1215  rt2x00_register_read(rt2x00pci, CSR21, &flags);
1216 
1217  /*
1218  * Clear data flags.
1219  */
1220  rt2x00_set_field32(&flags, CSR21_EEPROM_DATA_IN, 0);
1221  rt2x00_set_field32(&flags, CSR21_EEPROM_DATA_OUT, 0);
1222 
1223  /*
1224  * Start writing all bits.
1225  */
1226  do{
1227  /*
1228  * Only set the data_in flag when we are at the correct bit.
1229  */
1230  rt2x00_set_field32(&flags, CSR21_EEPROM_DATA_IN, (data & mask) ? 1 : 0);
1231 
1232  rt2x00_register_write(rt2x00pci, CSR21, flags);
1233 
1234  rt2x00_eeprom_pulse_high(rt2x00pci, &flags);
1235  rt2x00_eeprom_pulse_low(rt2x00pci, &flags);
1236 
1237  /*
1238  * Shift to next bit.
1239  */
1240  mask >>= 1;
1241  } while(mask);
1242 
1243  rt2x00_set_field32(&flags, CSR21_EEPROM_DATA_IN, 0);
1244  rt2x00_register_write(rt2x00pci, CSR21, flags);
1245 }
1246 
1247 static void
1248 rt2x00_eeprom_shift_in_bits(const struct _rt2x00_pci *rt2x00pci, u16 *data) {
1249 
1250  u32 flags = 0x00000000;
1251  u8 counter = 0x00;
1252 
1253  rt2x00_register_read(rt2x00pci, CSR21, &flags);
1254 
1255  /*
1256  * Clear data flags.
1257  */
1258  rt2x00_set_field32(&flags, CSR21_EEPROM_DATA_IN, 0);
1259  rt2x00_set_field32(&flags, CSR21_EEPROM_DATA_OUT, 0);
1260 
1261  /*
1262  * Start reading all 16 bits.
1263  */
1264  for(counter = 0; counter < 16; counter++){
1265  /*
1266  * Shift to the next bit.
1267  */
1268  *data <<= 1;
1269 
1270  rt2x00_eeprom_pulse_high(rt2x00pci, &flags);
1271 
1272  rt2x00_register_read(rt2x00pci, CSR21, &flags);
1273 
1274  /*
1275  * Clear data_in flag and set the data bit to 1 when the data_out flag is set.
1276  */
1277  rt2x00_set_field32(&flags, CSR21_EEPROM_DATA_IN, 0);
1278  if(rt2x00_get_field32(flags, CSR21_EEPROM_DATA_OUT))
1279  *data |= 1;
1280 
1281  rt2x00_eeprom_pulse_low(rt2x00pci, &flags);
1282  }
1283 }
1284 
1285 static u16
1286 rt2x00_eeprom_read_word(const struct _rt2x00_pci *rt2x00pci, const u8 word) {
1287 
1288  u32 flags = 0x00000000;
1289  u16 data = 0x0000;
1290 
1291  /*
1292  * Clear all flags, and enable chip select.
1293  */
1294  rt2x00_register_read(rt2x00pci, CSR21, &flags);
1295  rt2x00_set_field32(&flags, CSR21_EEPROM_DATA_IN, 0);
1296  rt2x00_set_field32(&flags, CSR21_EEPROM_DATA_OUT, 0);
1297  rt2x00_set_field32(&flags, CSR21_EEPROM_DATA_CLOCK, 0);
1298  rt2x00_set_field32(&flags, CSR21_EEPROM_CHIP_SELECT, 1);
1299  rt2x00_register_write(rt2x00pci, CSR21, flags);
1300 
1301  /*
1302  * kick a pulse.
1303  */
1304  rt2x00_eeprom_pulse_high(rt2x00pci, &flags);
1305  rt2x00_eeprom_pulse_low(rt2x00pci, &flags);
1306 
1307  /*
1308  * Select the read opcode and bus_width.
1309  */
1310  rt2x00_eeprom_shift_out_bits(rt2x00pci, EEPROM_READ_OPCODE, 3);
1311  rt2x00_eeprom_shift_out_bits(rt2x00pci, word, rt2x00pci->eeprom_width);
1312 
1313  rt2x00_eeprom_shift_in_bits(rt2x00pci, &data);
1314 
1315  /*
1316  * Clear chip_select and data_in flags.
1317  */
1318  rt2x00_register_read(rt2x00pci, CSR21, &flags);
1319  rt2x00_set_field32(&flags, CSR21_EEPROM_DATA_IN, 0);
1320  rt2x00_set_field32(&flags, CSR21_EEPROM_CHIP_SELECT, 0);
1321  rt2x00_register_write(rt2x00pci, CSR21, flags);
1322 
1323  /*
1324  * kick a pulse.
1325  */
1326  rt2x00_eeprom_pulse_high(rt2x00pci, &flags);
1327  rt2x00_eeprom_pulse_low(rt2x00pci, &flags);
1328 
1329  return data;
1330 }
1331 
1332 #endif /* RT2500PCI_H */
rtdm_lock_t
ipipe_spinlock_t rtdm_lock_t
Lock variable.
Definition: driver.h:551